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ls2k0300 specification

processor core

64-bit dual-issue superscalar la264 cores, based on loongarch

frequency

1ghz

high-speed cache

32kb l1 instruction cache and 32kb l1 data cache, supports ecc; 512kb l2 shared cache, supports ecc

memory controller

16-bit ddr4-1600 controllers; supporting ecc

high-speed i/o

2×usb 2.0, 2×gmac, 1×lcd display

other i/o

1 i2s, 4 can-fds, 4 spis, 2 qspis, 2 emmcs, 2 sdios, 1 lio, 8-channel adc, 4 i2cs, 10 uarts, 4 pwms, 3 sets of timer, 106 gpios, rtc, hpet, jtag, etc.

packaging

12mm×12mm fc-csp package with 286 pins

power management

supporting dynamic frequency scaling in processor core clock domains;supporting dynamic shutdown of the clocks of main modules

typical power consumption

<1w@1ghz

ls2k0300 manual

ls2k0300 application

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